library verilog;
use verilog.vl_types.all;
entity pmi_ram_dq is
    generic(
        pmi_addr_depth  : integer := 512;
        pmi_addr_width  : integer := 9;
        pmi_data_width  : integer := 18;
        pmi_regmode     : string  := "reg";
        pmi_gsr         : string  := "disable";
        pmi_resetmode   : string  := "sync";
        pmi_optimization: string  := "speed";
        pmi_init_file   : string  := "none";
        pmi_init_file_format: string  := "binary";
        pmi_write_mode  : string  := "normal";
        pmi_family      : string  := "EC";
        module_type     : string  := "pmi_ram_dq"
    );
    port(
        Data            : in     vl_logic_vector;
        Address         : in     vl_logic_vector;
        Clock           : in     vl_logic;
        ClockEn         : in     vl_logic;
        WE              : in     vl_logic;
        Reset           : in     vl_logic;
        Q               : out    vl_logic_vector
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of pmi_addr_depth : constant is 1;
    attribute mti_svvh_generic_type of pmi_addr_width : constant is 1;
    attribute mti_svvh_generic_type of pmi_data_width : constant is 1;
    attribute mti_svvh_generic_type of pmi_regmode : constant is 1;
    attribute mti_svvh_generic_type of pmi_gsr : constant is 1;
    attribute mti_svvh_generic_type of pmi_resetmode : constant is 1;
    attribute mti_svvh_generic_type of pmi_optimization : constant is 1;
    attribute mti_svvh_generic_type of pmi_init_file : constant is 1;
    attribute mti_svvh_generic_type of pmi_init_file_format : constant is 1;
    attribute mti_svvh_generic_type of pmi_write_mode : constant is 1;
    attribute mti_svvh_generic_type of pmi_family : constant is 1;
    attribute mti_svvh_generic_type of module_type : constant is 1;
end pmi_ram_dq;
